FIG. 1 is a block diagram illustrating a computer system 101, implementing a Direct Memory Access controller (referred to hereinafter as “DMA”) according to one embodiment of the invention. A core processor 102 and a DMA controller 103 both access data stored in the system's main memory 104. A Memory Interface Unit (“MIU”) 105 is used as an interface to the memory, enabling the DMA controller and the core processor to access data stored therein. The main memory 104 can be divided into several address spaces such as a data memory space 106 and a program memory space 107. Among its other roles, the MIU 105 prevents conflicts resulting when the core processor 102 and the DMA controller 103 try to access the same memory address at the same time. Data is channeled between the DMA controller 103 and the MIU 105 via a data bus 108 and between the MIU 105 and the core processor 102 via a data bus 109. Likewise, data is channeled between the MIU 105 and the data memory space 106 via a data bus 110 and between the MIU 105 and the program memory space 107 via a data bus 111.
During processing it is often required to rearrange data and/or to move data segments from one location in memory to another location, i.e. “data transfer”. Data transfer can be performed by the core processor 102, however, it is considered as a bottleneck to the core processor's operation. In the absence of a DMA controller 103, the core processor 102 dedicates timeslots for memory management, which would otherwise be dedicated to core processing computations. Therefore, it is the responsibility of the DMA controller 103 to manage and transfer data stored in memory, memory management that is performed in parallel to the core processor's operation. The DMA controller 103 transfers data from a source location to a destination location, or in other words, from source addresses to destination addresses.
The core processor 102 then accesses the data in the destination location, performing operations thereon. Sometimes it may happen that the core processor 102 and the DMA controller 103 both try to access the same memory address at the same time, a situation that gives rise to a conflict whose result is indefinite. In order to prevent such conflicts from occurring, memory access (done by the DMA controller or by the core processor) is performed by the Memory Interface Unit (MIU) 105.
Operation of microprocessors (such as the core processor 102) and other hardware components (such as the DMA controller 103) can be disabled/enabled in several known ways. For example, U.S. Pat. No. 5,978,860 (“System and method for disabling and re-enabling at least one peripheral device in a computer system by masking a device-configuration-space-access-signal with a disable or re-enable signal”, Dell USA. L.P., published 1999) discloses a system and a method for disabling and re-enabling peripheral devices (PDs) in a computer system. The system includes a CPU, a host bus coupled to the CPU, a host-bus-to-peripheral-device-bus (HB/PDB) bridge coupled to the host bus, at least one PD, at least one peripheral, device bus coupling the HB/PDB bridge and at least one PD. The system also includes a device, typically in the form of a digital gate, for selectively disabling and re-enabling at least one PD. The method of U.S. Pat. No. 5,978,860 operates in connection with a computer system having a CPU, a HB/PDB bridge coupled to the CPU and capable of sending a device-configuration-space-access-signal (DCSAS) to the DCSAS input pin of a target PD when attempting an access operation, such as a read or a write operation, on the target PD, and one or more system I/O registers having a CONFIG ENABLE bit that reflects a user's request to disable or re-enable a PD. The method intercepts the DCSAS before it reaches the DCSAS input pin of the target PD, provides the intercepted DCSAS to the input of a digital gate such as an AND gate, provides a signal corresponding to the CONFIG ENABLE bit to the input of the same digital gate, and delivers the resulting output signal from the digital gate to the DCSAS input pin of the target PD.
In addition, during development of software and hardware systems, it is sometimes required to debug the operation of the core processor 102 and the DMA controller 103.
Currently in the art there are several methods that allow debugging operation of a DMA controller. For example, EP 927,938 (“Data transfer method and device”, published 1999, assigned to Sony Computer Entertainment Inc) discloses debugging of a system which performs DMA transfer between different buses through a buffer. In EP 927,938, a first bus and a second bus are connected through a bus repeater, which has a buffer memory and two DMA (direct memory access) controllers that are connected to the first and second buses, respectively. The bus repeater can send DMA requests to the DMA controllers, and two CPUs can mask those DMA requests. A first of the two DMA controllers transfers data on the first bus to and from a buffer memory in the bus repeater, and the second DMA controller performs DMA transfer between the buffer memory and the second bus. A first of the two CPUs masks the DMA requests of the bus repeater and accesses the buffer directly to check the DMA function.
JP 1142848 (“Address trapping circuit”, published 1989, assigned to NEC Corp) discloses a method for checking the normality of data during data transfer by latching data on a data bus with an address signal outputted from a register circuit coincident with an address signal outputted from a direct memory access (DMA) controller to stop DMA operation.
In addition, it is possible to halt the operation of a core processor 102, for example in order to debug its operation, a procedure referred to as a breakpoint. However, when the core processor is halted, the DMA controller 103 can continue transferring data. In such case, the state of the registers and buses, such as the buses 108, 110 and 111 (together composing “data state”) can change while debugging, and the developer can get wrong impression of the data state that characterizing the system at any step. Thus, it would be clearly be desirable to solve this drawback by providing a way to halt the DMA when halting the CPU.
In addition, when halting the DMA, in any method known in the art, it is sometimes preferred that the core processor halts as well, preventing it from modifying, for example, the state of the memory or the buses (such as buses 109, 110 and 111). That is, mutual breakpoint capabilities are beneficial for debugging a is computing system including a DMA controller.